Common Source Amplifier

Fig. 23 shows the circuit of a common source n-channel JFET amplifier.

When the positive half cycle of applied input signal voltage v_gs is superimposed on V_GG, then the gate source voltage becomes less negative. As a result of this, the drain current increases. Since drain current flows through R_L, so the voltage drop across R_L (= I_d R_L) also increases. The output voltage of common source amplifier, V_O = V_DD – I_dR_L decreases.

On the hand, when negative half cycle of applied input signal voltage v_gs is superimposed on V_GG, then the gate source voltage becomes more negative. As a result of this, the drain current and hence the voltage drop across R_L decreases.

Consequently, the output voltage increases. The input voltage at the gate is 180^o out of phase with the output voltage at the drain.

A small change in the input voltage causes a large change in the output voltage, hence the applied signal is amplified.

Voltage Gain in Common source amplifier

The equivalent circuit of fig. 23, is shown in fig. 24. The equivalent circuit consists of a current source g_m v_gs and drain resistance r_d.

Since r_d and R_L are parallel, so their equivalent resistance is given by

The output voltage is given by

Using eqn. (1), we get

Negative sign shows that V_o is 180^o out of phase with the input voltage (v_gs)

Voltage gain (A_V) is defined as

Using eqn. (2), we get