Fig. 23 shows the circuit of a common source n-channel JFET amplifier.
When the positive half cycle of applied input signal voltage vgs is superimposed on VGG, then the gate source voltage becomes less negative. As a result of this, the drain current increases. Since drain current flows through RL, so the voltage drop across RL (= Id RL) also increases. The output voltage of common source amplifier, VO = VDD – IdRL decreases.
On the hand, when negative half cycle of applied input signal voltage vgs is superimposed on VGG, then the gate source voltage becomes more negative. As a result of this, the drain current and hence the voltage drop across RL decreases.
Consequently, the output voltage increases. The input voltage at the gate is 180o out of phase with the output voltage at the drain.
A small change in the input voltage causes a large change in the output voltage, hence the applied signal is amplified.
Voltage Gain in Common source amplifier
The equivalent circuit of fig. 23, is shown in fig. 24. The equivalent circuit consists of a current source gm vgs and drain resistance rd.
Since rd and RL are parallel, so their equivalent resistance is given by
The output voltage is given by
Using eqn. (1), we get
Negative sign shows that Vo is 180o out of phase with the input voltage (vgs)
Voltage gain (AV) is defined as
Using eqn. (2), we get
